1. Field of the Invention
The present invention relates to the field of data storage. More particularly, the present invention relates to a physical configuration of a magnetic tunnel junction (MTJ) device memory cell.
2. Description of the Related Art
U.S. Pat. No. 5,640,343 to Gallagher et al. discloses two configurations of a magnetic tunnel junction (MTJ) device memory cell. The first configuration, shown in FIGS. 1B and 1C of U.S. Pat. No. 5,640,343, represents an ideal cross point array structure that uses a thin film diode. The second configuration, shown in FIGS. 10A-10C, includes a buried row line that uses a single crystal silicon diode, but requires an additional global row line to be formed on top of the memory cell.
The quality of thin film diodes limits the first configuration to low sense currents and, consequently, a slower operational performance. The second configuration has a large spacing between the global row line and the magnetic element that requires a larger current through the row line when writing the cell than that through the row line of the first configuration. Additionally, the safety margin associated with the second configuration for avoiding writing of an adjacent cell is small and, with variability in materials, the second configuration has insufficient margin for operating cells one at a time in a large dense array. The first configuration similarly has a large spacing between the MTJ device and the row line, caused by the intervening diode, which reduces the write margin.
Consequently, what is needed is an MTJ memory cell configuration that has an improved write margin and a lower write current over conventional MTJ memory cell configurations, while also providing a smaller cell size.